1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a thin film transistor and a method for fabricating the same in which a sell alignment method is used to form an offset region and source and drain electrodes.
2. Discussion of the Related Art
A thin film transistor (hereinafter referred to as a TFT) is used in an SRAM cell of over 1M class instead of a CMOS load transistor or a load resistor. It is used as a switching device that switches picture data signals in each pixel. In particular, in case of an SRAM cell in which a PMOS TFT is used as a load transistor, off-current is reduced and on-current is increased so that the power consumption is diminished and that the memory characteristics are enhanced. Thus SRAM cells with good qualities can be realized.
An offset region is an important element for stable performance of an SRAM cell. It matters how precisely an offset region is formed. That is, the less it is modified in its process, the more precisely it is formed.
A conventional TFT and a conventional method for fabricating the same will be described with reference to the accompanying drawings.
FIG. 1 is a cross-sectional view showing the structure of a conventional TFT, which includes an insulating layer 21, a gate electrode 22a formed on a predetermined area of the insulating layer 21, a gate insulating film 24 formed on the insulating film 24 including the gate electrode 22a, a drain electrode D formed on the gate insulating film 24 and spaced apart from the gate electrode 22a, a source electrode S, in opposition to the drain electrode 22a, formed on the gate insulating film 24 to overlap the gate electrode 22a, and a channel region I and an offset region II formed on the gate insulating film 24 between the source electrode S and the drain electrode D. Herein, the offset region II is placed between the drain electrode D and the gate electrode 22a.
A conventional method for fabricating the above-mentioned TFT will be described with reference to the accompanying drawings.
Referring initially to FIG. 2A, a first polysilicon layer 22 for a gate electrode of the TFT is formed on an insulating layer 21. A first photoresist film 23 is coated on the first polysilicon layer 22 and is then patterned with an exposure and development process to form a pattern for a gate electrode.
Referring to FIG. 2B, thereafter, using this pattern as a mask, the first polysilicon layer 22 is selectively removed to form a gate electrode 22a.
Referring to FIG. 2C, a gate insulating film 24, which is a silicon oxide film, is deposited on the insulating layer 21 including the gate electrode 22a. Next, a second polysilicon layer 25 is formed on the gate insulating film 24 and then a second photoresist film 26 is coated on the second polysilicon layer 25.
Referring to FIG. 2D, the second photoresist film 26 is patterned for formation of channel and offset regions so as to form a mask pattern 26a. Using the mask pattern 26a, impurity ions are implanted to form a source electrode S partially overlapping the gate electrode 22a and a drain electrode D spaced apart from the gate electrode 22a by a predetermined distance. Consequently, the overall process for fabricating the TFT is completed.
However, the conventional TFT and the conventional fabricating method thereof have the following problems. Since processes using masks are necessary in forming source and drain electrodes and channel and offset regions, the overall process becomes complicated. Further, in mask alignment, misalignment might be caused so that there is modified an offset region that is an important element for stable performance of an SRAM cell.